1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor wafer, and particularly to a fabrication method of a semiconductor wafer that includes trenches formed in a first conductivity type semiconductor substrate, and has a structure in which the trenches are filled with an epitaxial film composed of a second conductivity type semiconductor.
2. Description of the Related Art
Generally, semiconductor devices are divided into a lateral device having electrodes formed on one side, and a vertical device having electrodes formed on both sides. In the vertical semiconductor device, the direction in which the drift current flows in the on state is the same as the direction in which the depletion layer is extended by a reverse bias voltage in the off state. In an ordinary planar n-channel vertical MOSFET, the drift layer with the high resistance operates as a region through which the drift current flows in the vertical direction in the on state. Accordingly, reducing the length of the current path of the drift layer can decrease the drift resistance, thereby offering an advantage of being able to reduce the effective on-resistance of the MOSFET.
On the other hand, since the drift layer becomes a depletion region in the off state to increase the withstand voltage, the thin drift layer reduces the withstand voltage. On the contrary, as for a semiconductor device with a high withstand voltage, since the drift layer is thick, the on-resistance is large, thereby increasing the loss. Thus, there is a tradeoff between the on-resistance and the withstand voltage.
It is known that the tradeoff also applies to semiconductor devices such as MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), bipolar transistors and diodes. In addition, the tradeoff is also seen in the lateral semiconductor devices in which the direction in which the drift current flows in the on state differs from the direction in which the depletion layer extends in the off state.
As devices to solve the foregoing problem with the tradeoff, super-junction semiconductor devices are known which include a drift layer having a parallel pn structure composed of the alternate junctions of n-type semiconductor regions and p-type semiconductor regions with increased impurity concentrations (refer to European patent application laid-open No. 0053854, U.S. Pat. Nos. 5,216,275 and 5,438,215, Japanese patent application laid-open No. 266311/1997). The semiconductor devices with such a structure can increase the withstand voltage in spite of the high impurity concentration of the parallel pn structure. This is because the depletion layer spreads in the off state in the lateral direction at the individual pn junctions of the parallel pn structure that extends in the vertical direction, and hence the drift layer is depleted in its entirety.
As for fabrication methods of producing the super-junction wafer used for the fabrication of the foregoing super-junction semiconductor devices, those that can lead to low cost and mass-producibility have been studied actively. For example, a method has been developed of forming trenches in the surface layer of a first conductivity type semiconductor substrate, followed by epitaxial growth of a second conductivity type semiconductor in the trenches. Alternatively, a method has been proposed of filling the trenches with an epitaxial film, followed by oxidizing its surface to eliminate the crystal defect in the epitaxial film near the center of upper part of the trenches (refer to Japanese patent application laid-open No. 340578/2000).
In addition, a method is proposed of forming the parallel pn structure at a narrow pitch by wet anisotropic etching (refer to Japanese patent application laid-open No. 168327/2001). To achieve the narrow pitch, it utilizes a (110) plane as its substrate surface, and forms the contact planes of the n-type semiconductor regions and the p-type semiconductor regions of the parallel pn structure such that they become (111) plane or its equivalent plane, that is, {111} plane, and extend in the [110] direction.
Alternatively, a method is proposed of growing a small amount of the epitaxial film in the trenches, followed by increasing the openings of the trenches by etching part of the epitaxial film, and by filling the trenches without leaving a cavity within the trenches by carrying out the epitaxial growth again (refer to Japanese patent application laid-open No. 196573/2001).
As for a method of forming the trenches, a method of carrying out first etching followed by second etching is proposed (refer to Japanese patent application laid-open No. 141407/2002). The first etching is performed on a semiconductor substrate surface using mixed gas plasma of silicon halide gas or boron halide gas with oxygen or nitrogen. The second etching is conducted using mixed gas plasma of halogen-containing gas with oxygen or nitrogen. The first etching forms the trenches such that their openings have gently sloping tapered planes, whereas the second etching forms them as steep trenches.
However, filling the trenches with the epitaxial film presents the following two problems. The first problem is that since the cleaning technique of the inner walls of the trenches is under development and immature at the present, a trace quantity of silicon oxide (SiOx, where X equals 0, 1 or 2) or amorphous silicon is left in the inner walls of the trenches. The immature cleaning technique can also bring about micro-scale or nano-scale surface roughness, which impairs the quality of the epitaxial film. It has been gradually found that the foreign matters or surface roughness can be removed to some extent by hydro-fluoric acid cleaning, plasma etcher or chemical dry etcher (CDE). However, it is difficult to remove them completely at the present. The second problem is that since the epitaxial film grown thickly around the openings of the trenches blocks the openings, a cavity is apt to be left in the trenches.
The foregoing literatures do not refer to the effect on the epitaxial growth brought about by the foreign matters or roughness on the inner walls of the trenches. For example, the method of forming the trenches disclosed in Japanese patent application laid-open No. 141407/2002 relates to a technique of forming device isolation regions by filling the trenches with the oxide film, or forming an oxide film on the inner walls of the trenches as in trench-type MOSFETs or trench-type capacitors, rather than a technique that fills the trenches with the epitaxial film. Thus, it considers nothing about the foreign matters or roughness on the inner walls of the trenches.